Designing SOCs with Configured Cores

8.2. Diamond 212GP Controller Core Interfaces

The Diamond 212GP controller core has a number of interfaces for high-bandwidth I/O, as shown in Figure 8.2. These interfaces include a 32-bit implementation of the Xtensa PIF (main processor interface) bus and separate memory interfaces for one local instruction memory block and one local data memory block. Each of the local-memory interfaces can accommodate memories as large as 128 Kbytes. In addition, the Diamond 212GP core has an XLMI port with a 128-Kbyte address space. The XLMI port can be used to control a local memory block, which gives the Diamond 212GP controller a maximum of 384 Kbytes of local memory.

Figure 8.2. The Diamond 212GP controller core has two 32-bit memory-interface buses ...