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Designing SOCs with Configured Cores by Steve Leibson

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8.7. The Diamond 212GP Controller’s Cache Interfaces

Most RISC processors including the Diamond 212GP core use cache memories—fast, small RAM arrays—to buffer the processor from the slower and larger main memories generally located external to the processor core or the SOC. The Diamond 212GP core’s caches store the data and instructions that a program is immediately using, while the majority of other data resides in slower main memory (RAM or ROM). In general, the Diamond 212GP core accesses instruction and data caches simultaneously, which maximizes processor bandwidth and efficiency.

The Diamond 212GP controller incorporates a pre-configured version of the Xtensa cache controller that operates separate, 2-way set-associative, 8-Kbyte instruction ...

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