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Designing SOCs with Configured Cores by Steve Leibson

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9.2. Diamond 232L CPU Core Interfaces

As shown in Figure 9.2, the Diamond 232L CPU core has a 32-bit implementation of the Xtensa PIF (main processor interface) bus and separate interfaces for the 4-way set-associative instruction and data caches. Unlike the 108Mini and 212GP controller cores, the Diamond 232L CPU core does not have interfaces for local memories or an XLMI port. All memories (except for the instruction and data caches) and any other system devices attach to the Diamond 232L CPU through its PIF bus.

Figure 9.2. The Diamond 232L CPU core has a 32-bit implementation of the Xtensa PIF (main processor interface) bus and separate interfaces for the 4-way set-associative instruction and data caches.

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