O'Reilly logo

Designing SOCs with Configured Cores by Steve Leibson

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

10.1. The Diamond 570T: A High-Performance CPU Core

The Diamond 570T CPU architecture contains all of the basic elements of the Xtensa ISA. It has a 32-entry general-purpose register file, a 5-stage execution pipeline and 32-bit addressing. It has two additional execution pipelines giving the processor core the ability to execute three independent instructions per clock. The Diamond 570T CPU’s three execution pipelines are not symmetric, as shown in Figure 10.2. The first execution pipeline, associated with operation slot 0, contains the base Xtensa ALU, a 32-bit multiplier, a branch unit, and the processor’s load/store unit.

Figure 10.2. The Diamond 570T processor core implements a high-performance, 3-way superscalar, 32-bit RISC CPU while ...

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required