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Designing SOCs with Configured Cores by Steve Leibson

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10.4. The Diamond 570T CPU’s Cache Interfaces

The Diamond 570T CPU core’s data and instruction caches store data and instructions that a program is immediately using, while the rest of the data and program reside in slower main memory—RAM or ROM. In general, the Diamond 570T CPU core can access instruction and data caches simultaneously, which maximizes processor bandwidth and efficiency.

The Diamond 570T CPU incorporates a pre-configured version of the Xtensa cache controller that operates separate, 16-Kbyte, 2-way, set-associative instruction and data caches. Note that the width of the data buses to the Diamond 570T CPU’s instruction and data caches is 64 bits rather than the 32-bit widths for the caches discussed in earlier chapters. The data ...

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