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Designing SOCs with Configured Cores by Steve Leibson

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13.3. On-Chip Communications for SOCs

Previous chapters in this book have discussed a number of ways to connect multiple processors together to achieve high bandwidths. Some of these include the use of bridged buses (shown in Figure 13.7) and pipelined data-flow architectures (or systolic-processing systems) using FIFO-based inter-processor communications (Figure 13.8). Many such possible architectures exist.

Figure 13.7. Bridged-bus, MPSOC architecture.
Figure 13.8. Systolic, MPSOC architecture.

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