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Designing SOCs with Configured Cores by Steve Leibson

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14.1. A Viable Alternative to Manual RTL Design and Verification

Configurable processors like Tensilica’s Xtensa cores can be used as alternatives to manually-coded RTL blocks. Application-tailored Xtensa cores use the same data-path structures as traditional RTL blocks: deep pipelines, parallel execution units, task-specific state registers, and wide data buses to local and global memories. Tailored, task-specific processors can sustain the same high-computation throughput and support the same data interfaces as RTL hardware designs.

Migrating an SOC design team’s design style from heavy use of RTL data paths and finite state machines (FSMs) to application-tailored processors with firmware control has many important implications:

  1. Flexibility: ...

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