Designing SOCs with Configured Cores

15.1. Grand Challenges and Disaster Scenarios

SOC designers have become increasingly unable to fully exploit all of the transistors available to them starting with the 90-nm process node in 2003–2004, as shown in Figure 15.1. The figure incorporates data presented by Gary Smith of Gartner Dataquest at DAC 2003 that is based on ITRS survey data and shows that silicon-manufacturing capacity and SOC-design capacity have tracked well since the widespread adoption of hardware-description languages (HDLs) in the early 1990s during the 1-micron era. HDLs first appeared years before, in the early 1980s, but did not become popular until gate- and transistor-level schematic drafting—the well-established IC-design method of the day—could no longer handle ...