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Designing SOCs with Configured Cores by Steve Leibson

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15.1.3. SOC Disaster Scenario 3: Loss of Manufacturability

The current SOC-design style assumes a perfect chip. Flawed chips are simply thrown away, a decades-old practice. Memory and FPGA vendors have long designed redundant circuits in the form of extra rows and columns into their products to boost manufacturing yields. Nanometer silicon manufacturing can no longer provide the luxury of perfect chips to SOC designers.

One of the wonders of the semiconductor industry is that it has pushed manufacturing yields high enough to shield application-specific integrated circuit (ASIC) and SOC designers from the need to develop manufacturable systems for their chip designs. As system designers move to higher design-abstraction levels and become further ...

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