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Designing SOCs with Configured Cores by Steve Leibson

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15.1.4. SOC Disaster Scenario 4: Excessive Signal Interference

Long on-chip interconnects, high-frequency signals, sharp clock edges, global clocking, and global buses are all part of the system-design status quo. The result of this design style is growing electrical and magnetic interference between on-chip signals. Physical design rules for wire spacing and inductance management have previously sufficed to keep this problem at bay. Nanometer silicon substantially increases this challenge.

Long buses interconnecting everything on a chip must go. Bus hierarchies are also in peril. Increased wire density makes victim signal wires even more susceptible to inductively and capacitively coupled noise. Repeaters and slew-rate control methods that ...

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