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Designing SOCs with Configured Cores by Steve Leibson

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15.2.2. Avoiding Disaster Scenario 2: Excessive System Power Dissipation

A processor-centric SOC-design style directly addresses issues related to system power dissipation. Current ad hoc system-design styles waste power in many ways. Design efforts directed at saving transistors through processor multitasking and similar schemes drive on-chip clock rates ever higher, which drastically increases power dissipation. This design style, which evolved when transistors were expensive and chip power levels were low, is no longer valid in the era of nanometer ICs. The use of one or two multitasked, high-speed processors in an SOC also emphasizes the use of large, highly capacitive, global buses which also dissipate excessive power.

The processor-centric ...

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