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Designing SOCs with Configured Cores by Steve Leibson

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15.2.3. Avoiding Disaster Scenario 3: Loss of Manufacturability

The semiconductor industry has a tried and true approach to dealing with manufacturability issues: make the chip as perfect as possible and bridge any remaining gap between real and desired device yields with redundant structures. Memory and FPGA vendors have successfully used this strategy for many years. They have long put redundant, fuse- and laser-programmable rows and columns into their device designs to maximize yields for a controlled increase in silicon cost.

SOC designers have been shielded from the need to consider redundancy in their designs. No longer. Fabrication defects will be a fact of life for all SOC designers at nanoscale-processing nodes. A processor-centric ...

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