
Exercises
471
8.21
(as stated in the text, as an approximation the delay can be obtained by the sum
of the delays in the critical path) for single precision and for double precision.
Pipeline the floating-point adder (for single precision and for double) for a
clock rate of 200 MHz. To account for clock skew and other delays, the stage
delay should not be larger than 80% of the clock cycle.
[Executing FLPT
addition and subtraction on
improved single-path implemen-
tation] Perform the following operations using the implementation of Figure 8.8.
Include the guard bits, perform all four rounding modes, and determine if there
is an exponent overflow. ...