19 VHDL Summary
Chapter Contents
19.1 About VHDL
19.2 Code Structure
19.3 Fundamental VHDL Packages
19.6 Operators
19.7 Attributes
19.8 Concurrent versus Sequential Code
19.9 Concurrent Code (WHEN, GENERATE)
19.10 Sequential Code (IF, CASE, LOOP, WAIT)
19.11 Objects (CONSTANT, SIGNAL, VARIABLE)
19.12 Packages
19.13 Components
19.14 Functions
19.15 Procedures
19.16 VHDL Template for FSMs
19.17 Exercises
Objective:
This chapter concisely describes the VHDL language and presents some introductory circuit synthesis examples. Its purpose is to lay the fundamentals for the many designs that follow in Chapters 20 and 21, for combinational circuits, and in Chapters 22 and 23, for sequential ...
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