Digital Logic Testing and Simulation, 2nd Edition

CHAPTER 9

Built-In Self-Test

9.1 INTRODUCTION

Numerous ATPG algorithms and heuristics have been developed over the years to test digital logic circuits. Some of these methods can trace their origins back to the very beginnings of the digital logic era. Unfortunately, they have proven inadequate to the task. Despite many novel and interesting schemes designed to attack test problems in digital circuits, circuit complexity and the sheer number of logic devices on a die continue to outstrip the test schemes that have been developed, and there does not appear to be an end in sight, as levels of circuit integration continue to grow unabated.

New methods for testing and verifying physical integrity are being researched and developed. Where once the need for concessions to testability was questioned, now, if there is any debate at all, it usually centers on what kind of testability enhancements should be employed. However, even with design-for-testability (DFT) guidelines, difficulties remain. Circuits continue to grow in both size and complexity. When operating at higher clock rates and lower voltages, circuits are susceptible to performance errors that are not well-modeled by stuck-at faults. As a result, there is a growing concern for the effectiveness as well as the cost of developing and applying test programs.

Test problems are compounded by the fact that there is a growing need ...