2

DRAM Cell Development

2.1    Introduction

Low cost per bit and high packing density of DRAMs are unmatched by any other semiconductor memory. Within the limitations of fabrication processes, mainly lithography, area of the memory cell layout is very crucial as it has direct impact on the performance and the cost. The initial-stage cell was a simpler entity, of course, in comparison to the complex products of today, in the form of a single access transistor and a storage capacitor laid side by side in two dimensions; it has been called a planar DRAM cell. Overall cell size continued to shrink without any serious obstacles till the 1–4 Mbit range. However, beyond that, shrinking of the cell in two dimensions became impracticable, because ...

Get Dynamic RAM now with the O’Reilly learning platform.

O’Reilly members experience live online training, plus books, videos, and digital content from nearly 200 publishers.