Electronic Design Automation

3.4.3. Logic BIST architectures

Several architectures for incorporating offline BIST techniques into a design have been proposed. These BIST architectures can be classified into two classes: (1) those that use the test-per-scan BIST scheme and (2) those that use the test-per-clock BIST scheme. The test-per-scan BIST scheme takes advantage of the already built-in scan chains of the scan design and applies a test pattern to the CUT after a shift operation is completed; hence, the hardware overhead is low. The test-per-clock BIST scheme, however, applies a test pattern to the CUT and captures its test response every system clock cycle; hence, the scheme can execute tests much faster than the test-per-scan BIST scheme but at an expense of more ...