Electronic Design Automation

13.2. Design Considerations

Consider a simple synchronous circuit that uses positive edge-triggered flip-flops (FF's) as the sequential elements controlled by a clock signal that has even duty cycle (i.e., a single-phase clocking scheme). We use S = {s¹,s², …, sⁿ} to denote the set of clock pins of flip-flops in the circuit, with sⁱ being the clock pin of flip-flop FFⁱ.

A pair of flip-flops is sequentially adjacent when only combinational logic exists between the two flip-flops. Let FFⁱ and FF^j be two sequentially adjacent flip-flops, with the output of FFⁱ being fed to the data input of FF^j through a combinational logic (see Figure 13.1). We say that FFⁱ is the launching flip-flop and FF^j is the capturing flip-flop.

FIGURE 13.1. A simple ...