Embedded SoPC Design with Nios II Processor and Verilog Examples

CHAPTER 16

SRAM AND SDRAM CONTROLLERS

While an FPGA device contains dedicated memory modules within the chip, its capacity is relatively small. Separate external memory devices are needed to support the larger storage requirement. On the DE1 board, there are an SRAM (static random access memory) device and an SDRAM (synchronous dynamic random access memory) device. In this chapter, we provide an overview of various types of memory and discuss the design and use of a memory controller, which is the circuit to read and write the external memory devices. Since the off-chip access introduces new types of delays, we also provide a brief overview of timing issues and clock management.

16.1 MEMORY RESOURCES OF DE1 BOARD

The Altera EP2C20 FPGA device and DE1 board provide several options for storage elements:

• EP2C20's D FFs (for registers): about 20K bits embedded in logic cells (LEs).
• EP2C20's embedded RAM: about 200K bits, configured as 52 4K-bit modules.
• off-chip SRAM device: about 4,000K bits, arranged as a 256K-by-16 cell array.
• off-chip SDRAM device: about 64,000K bits, arranged as a 4M-by-16 cell array.

These memory options exhibit a trade-off between cost and performance. A D FF is the fastest and most versatile option but requires the most silicon area and thus has the highest per-bit cost. It is only feasible for small, fast buffers. On the other hand, an SDRAM cell occupies the smallest silicon area and has the lowest per-bit cost but has the slowest access speed. Thus, it ...