Embedded Systems: Hardware, Design and Implementation

8

Real-Time Configurable Phase-Coherent Pipelines

ROBERT L. SHULER, JR., and DAVID K. RUTISHAUSER

8.1 INTRODUCTION AND PURPOSE

Field-programmable gate array (FPGA) development tools provide many computational functions, such as floating-point operations, as modules with the option of making them pipelines. Other user-implemented functions, such as filters and transforms, are easily and often implemented in FPGAs using a pipelined architecture. This allows high clock rates to be used for complex operations and high data throughputs to be obtained. This of course works by exploiting parallelism, in which each stage of the pipeline is simultaneously working on a different set of data. The data for a particular operation are said to flow through the pipe.

8.1.1 Efficiency of Pipelined Computation

Computations implemented in pipelined hardware can be very efficient. Not only are they fast, but inherently they have less overhead than sequential processors, and studies have shown that FPGA implementations of floating-point algorithms offer significant power advantages [1]. However, the effort to create the design, and especially the effort to modify and maintain it, can be much higher than alternative techniques. One method is to define a direct datapath, or systolic array—a connected graph of computational units and delay lines with everything timed so that the results of several pipeline units will appear at the correct clock cycle for input into another pipeline unit, until finally ...