Low Overhead Radiation Hardening Techniques for Embedded Architectures



As device sizes continue to shrink into the nano regime, the reliability of circuits, devices, as well as the architectures that use these becomes a very critical issue. Perhaps one of the most critical impacts of technology scaling is the significant reduction in the device threshold values. In other words, the amount of critical charge required for changing the state of a device or a circuit node from 1–0 or 0–1 has dropped considerably. As a result, modern high-performance logic and memory circuits become increasingly susceptible to transient errors caused due to charged particles striking sensitive circuit nodes. These phenomena associated with faulty behavior of the circuit due to particle strikes are known as soft errors. Soft errors can be classified as single event errors (SEEs) and single event upset (SEU) [1]. The former consists of a permanent defect or error induced by a particle strike and is an issue more efficiently handled at the device level. SEUs, on the other hand, involve a temporary flipping of states of the circuit and can be rectified using circuit-level as well as top-level architectural techniques.

After being initially observed by Intel in their memory designs, this problem of SEUs was thought of as being restricted to space applications. Space-based electronics are constantly required to work in environments ...

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