Emerging Nanoelectronic Devices

14Re-Invention of FET

Toshiro Hiramoto

Institute of Industrial Science, The University of Tokyo, Japan

14.1 Introduction

The silicon metal oxide semiconductor field effect transistor (MOSFET) for very large scale integration (VLSI) has been scaled down for more than 40 years in order to attain higher speed, lower power, higher integration, and lower cost. The gate length has reached as small as 20 nm and more than a billion transistors are now integrated in a single chip. The silicon devices are certainly in both the nanometer regime and the giga-scale integration regime. It is predicted in the 2011 version of the International Technology Roadmap for Semiconductors (ITRS) [1] that FET will continue to miniaturize and its gate length will become less than 10 nm in 2022 in production. The semiconductor technologies will continue to be the basis of the contemporary information-oriented society.

However, there are a lot of technical barriers to realize such small and giga-scale devices with higher performance and lower power dissipation. It is now well recognized that simple scaling of conventional bulk MOSFETs will fail in the nanometer regime. Therefore, nonconventional MOSFETs with new transistor structures and/or new channel materials have been under development and even re-invention of new types of FETs has been pursued at research level.

In this chapter, the historical trend of MOSFETs in the past and the future trend predicted by ITRS are compared first in order to look ...