
6 Energy-Aware Memory Management: A CAD Approach
DRAM Banks
Exec
Units
Memory
Level 0
1–16 K
Memory
Level 1
4–64 K
Memory
Level 2
16–1024 K
Memory
Control
& Buffer
Datapath
Control
& Buffer
Processor Chip
Processor Bus
Figure 1.2 Memory hierarchy example [15].
c
2000 IEEE.
The memory optimization targeted by this book starts from a given high-
level behavioral specification (therefore, the memory access pattern is fixed)
and aims to produce an energy-efficient customized memory hierarchy. Notice
that the memory optimization problem could be addressed in different ways:
for instance, one may assume a fixed memory hierarchy and modify the access
pattern of the target application ...