
Chapter 5
Storage Allocation for
Streaming-Based Register File
Praveen Raghavan
SSET, IMEC vzw, Heverlee, Belgium
Francky Catthoor
SSET, IMEC vzw, Leuven, Belgium
Contents
5.1 Stream Register File: Why and How .................................152
5.1.1 Register files and their nonuniformal access patterns ........152
5.1.2 Very wide register: a streaming foreground memory
architecture ...................................................154
5.1.2.1 Data (background) memory organization
and interface .........................................155
5.1.2.2 Foreground memory organization ....................156
5.1.2.3 Connectivity between VWR and datapath .......... ...