
156 Energy-Aware Memory Management for EMSs
Column Decoder and Precharge Logic
Row Addr Position No. Words
SA Activation
Logic
Word
Word
Pre-decoder
Address
Sense Amplifiers
SRAM Array
To/From VWR (SPW bits Wide)
Figure 5.3 VWR and scratchpad organization.
with connecting multiple narrow memories in parallel, the gains are still sub-
stantial. Concatenating multiple narrower memories still results in gains at
the processor level as wider loads/stores implies fewer address computations
at run-time, fewer load/store instructions and fewer decodes required even for
the register file.
5.1.2.2 Foreground memory organization
The proposed register file has single ported ...