
Chapter 7
Leakage Current Mechanisms and
Estimation in Memories and Logic
Ashoka Sathanur
IMEC, Eindhoven, The Netherlands
Praveen Raghavan
IMEC, Heverlee, Belgium
Stefan Cosemans
K.U. Leuven, Leuven, Belgium
Wim Dahaene
K.U. Leuven, Leuven, Belgium
Contents
7.1 Introduction ..........................................................240
7.2 Leakage Current Mechanisms ........................................240
7.2.1 Subthreshold leakage ..........................................240
7.2.2 Gate leakage ...................................................244
7.2.3 Junction tunneling leakage ....................................245
7.2.4 Leakage in different technologies ...