254 Energy-Aware Memory Management for EMSs
7.4.3.1 Leakage of memory core
As shown in [12] the leakage of the memory core can be approximately
written as
I
core
= N
rows
· N
columns
· W
bitcell
· I
leak,tech
(7.16)
Here N
rows
and N
columns
denote the number of rows and columns in the
SRAM memory, respectively. W
bitcell
denotes the effective width of each leak-
ing bit cell. Note that this factor is bit cell implementation dependent. This
equation shows that leakage of an SRAM memory core of a given size, tech-
nology, and operating conditions is clearly dependent on the implementation
of its bit cell.
7.4.3.2 Leakage of drivers
The number of drivers clearly depends on the SRAM architecture. In an archi-
tecture that has fully subdivided wordlines, there is one driver ...