Skip to Main Content
Energy-Aware Memory Management for Embedded Multimedia Systems
book

Energy-Aware Memory Management for Embedded Multimedia Systems

by Florin Balasa, Dhiraj K. Pradhan
November 2011
Intermediate to advanced content levelIntermediate to advanced
359 pages
11h 16m
English
Chapman and Hall/CRC
Content preview from Energy-Aware Memory Management for Embedded Multimedia Systems
254 Energy-Aware Memory Management for EMSs
7.4.3.1 Leakage of memory core
As shown in [12] the leakage of the memory core can be approximately
written as
I
core
= N
rows
· N
columns
· W
bitcell
· I
leak,tech
(7.16)
Here N
rows
and N
columns
denote the number of rows and columns in the
SRAM memory, respectively. W
bitcell
denotes the effective width of each leak-
ing bit cell. Note that this factor is bit cell implementation dependent. This
equation shows that leakage of an SRAM memory core of a given size, tech-
nology, and operating conditions is clearly dependent on the implementation
of its bit cell.
7.4.3.2 Leakage of drivers
The number of drivers clearly depends on the SRAM architecture. In an archi-
tecture that has fully subdivided wordlines, there is one driver ...
Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Nanoelectronic Device Applications Handbook

Nanoelectronic Device Applications Handbook

James E. Morris, Krzysztof Iniewski
Networks on Chips

Networks on Chips

Giovanni De Micheli, Luca Benini, Davide Bertozzi, Israel Cidon, Kees Goossens, Kwanho Kim, Kangmin Lee, Se-Joong Lee, Srinivasan Murali, Hoi-Jun Yoo
UPC: DISTRIBUTED SHARED MEMORY PROGRAMMING

UPC: DISTRIBUTED SHARED MEMORY PROGRAMMING

Tarek El-Ghazawi, William Carlson, Thomas Sterling, Katherine Yelick
Strain-Engineered MOSFETs

Strain-Engineered MOSFETs

C.K. Maiti, T.K. Maiti

Publisher Resources

ISBN: 9781439814017