
Leakage Control in SoCs 267
vdd
cell
= 1 V
vss
cell
= 0 V
BL
BL
Q = “1” Q = “0”
WL = 0 V
WL = 0 V
V (BL) = 1 V V(BL) = 1 V
353
84
269
28
35
6
25 199
11
38
355
156
51
26
26
38
11
25
Figure 8.3 Leakage currents in a 90-nm HVT 6T SRAM cell at 27 degrees
Celsius. All transistors have W = 200 nm, L = Lmin. Supply voltage is 1 V.
their state during typical standby periods. This makes it impossible to apply
typical power shutoff techniques. Because the cell state is not predefined, state-
enforcing leakage reduction techniques such as zigzag super cutoff CMOS [8]
cannot be applied either.
Figure 8.3 shows the leakage currents in a 6T cell in the example 90 nm
technology at a supply