
Leakage Control in SoCs 277
L1 Instruction Memory
L0 Instruction Cluster
Loop Buffer
Register File
Main
Processor
Data Cluster
PC
LC
Register File
L1 Data Memory
F
U
F
U
F
U
F
U
F
U
F
U
Loop Buffer
Unified L2 Memory
External Memory
Figure 8.11 Basic processor architecture.
processor with its instruction memory, data memory, clustered register file,
and different issue slots. The following subsections show some of the techniques
to reduce the energy in such a platform within one core.
8.4.1 Register file
In processors, mostly the register files are clustered or centralized or
banked [23]. This is one of the most efficient ways to reduce power consump-
tion in the register file. Such a ...