xiv CONTENTS
10.8.4 Review of Excitation Tables 457
10.8.5 Design of Special-Purpose Flip-Flops and Latches 459
10.9 Latches and Flip-Flops with Serious Timing Problems: A Warning 461
10.10 Asynchronous Preset and Clear Overrides 463
10.11 Setup and Hold-Time Requirements of Flip-Flops 465
10.12 Design of Simple Synchronous State Machines with Edge-Triggered Flip-
Flops: Map Conversion 466
10.12.1 Design of a Three-Bit Binary Up/Down Counter: D-to-T K-map
Conversion 466
10.12.2 Design of a Sequence Recognizer: D-to-JK K-map Conversion 471
10.13 Analysis of Simple State Machines 476
10.14 VHDL Description of Simple State Machines 480
10.14.1 The VHDL Behavorial Description of the RET D Flip-flop 480
10.14.2 The VHDL Behavioral Description of a Simple FSM ...