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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
PROBLEMS 293
(c) Implement the results of part (b) by making use of Eq. (6.22). Is an eq input
necessary?
6.29 Given the block symbol for a 4-bit cascadable comparator in Fig. 6.30 and with the
appropriate gate-minimum NAND/EQV/INV external logic, design a 5-bit cascadable
comparator. (Hint: Use the 1-bit comparator as the output (MSB) stage.)
6.30 Design a 4-bit even-parity detector with respect to logic 1 by using only XOR gates
(nothing else). Show how this result can be used to produce a 4-bit odd-parity detector
without adding additional hardware.
6.31 (a) Design a logic circuit that will detect a majority of seven inputs A, B, C, D, E,
F, and
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Publisher Resources

ISBN: 9780126912951