Skip to Main Content
Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
7.3 PROGRAMMABLE LOGIC ARRAYS 301
section would be required. Recall that the three-level logic circuit for the cascadable 2-bit
comparator in Fig. 6.28 has a gate/input tally of only 23/67.
7.3 PROGRAMMABLE LOGIC ARRAYS
Like the ROM, the PLA is an n-input/m-output device composed of an input ANDing stage
and a memory (ORing) output stage. Unlike the ROM, however, both stages of the PLA
are programmable, as indicated by the block diagram in Fig. 7.5. The AND matrix (array)
generates the product terms (p-terms), while the OR matrix ORs the appropriate product
terms together to produce the required SOP functions.
The dimensions of a PLA are specified by ...
Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Top-Down Digital VLSI Design

Top-Down Digital VLSI Design

Hubert Kaeslin
Engineering Physics

Engineering Physics

S. Mani Naidu
Analog Integrated Circuit Design, 2nd Edition

Analog Integrated Circuit Design, 2nd Edition

Tony Chan Carusone, David A. Johns, Kenneth W. Martin
Analog Circuit Design Volume Three

Analog Circuit Design Volume Three

Bob Dobkin, John Hamburger

Publisher Resources

ISBN: 9780126912951