
7.3 PROGRAMMABLE LOGIC ARRAYS 301
section would be required. Recall that the three-level logic circuit for the cascadable 2-bit
comparator in Fig. 6.28 has a gate/input tally of only 23/67.
7.3 PROGRAMMABLE LOGIC ARRAYS
Like the ROM, the PLA is an n-input/m-output device composed of an input ANDing stage
and a memory (ORing) output stage. Unlike the ROM, however, both stages of the PLA
are programmable, as indicated by the block diagram in Fig. 7.5. The AND matrix (array)
generates the product terms (p-terms), while the OR matrix ORs the appropriate product
terms together to produce the required SOP functions.
The dimensions of a PLA are specified by ...