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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
350 CHAPTER 8 / ARITHMETIC DEVICES AND ARITHMETIC LOGIC UNITS (ALUs)
FIGURE 8.15
The carry-save (CS) method of addition. (a) CS addition of four 4-bit numbers. (b) The CS adder
designed to add four 4-bit operands by using FAs a HA and a 4-bit R-C or CLA adder.
8.6 MULTIPLIERS
An n × m multiplier is an (n + m)input/(n + m)output device that performs the
logic equivalent of an n-bit×m-bit binary multiplication. Shown in Fig. 8.16a is the block
circuit symbol, and in Fig. 8.16b the operation format for a 4-bit ×4-bit multiplier that
follows Algorithm 2.10, given in Subsection 2.9.4. As indicated in the operation format the
8.6 MULTIPLIERS 351
FIGURE
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Publisher Resources

ISBN: 9780126912951