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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
8.7 PARALLEL DIVIDERS 353
FIGURE 8.19
The iterative carry-save (ICS) method with FAs, HAs, and a 4-bit CLA adder used to multiply two
4-bit operands. Partial products P
ij
are generated as in Fig. 8.18.
The iterative CS multiplier of Fig. 8.19 has the advantage of reduced computation time
compared to the R-C approach illustrated in Fig. 8.18. For n rows and 2n 1 columns of
partial products, the summation time for an iterative CS (ICS) multiplier is
t
ICS
= (n 2)t
FA
+ t
RC
, (8.10)
where t
FA
is the delay of a FA and t
RC
is the time required for the R-C adder to complete
the summation. In comparison, the summation time required for a multiplier that uses ...
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Publisher Resources

ISBN: 9780126912951