
8.7 PARALLEL DIVIDERS 353
FIGURE 8.19
The iterative carry-save (ICS) method with FAs, HAs, and a 4-bit CLA adder used to multiply two
4-bit operands. Partial products P
ij
are generated as in Fig. 8.18.
The iterative CS multiplier of Fig. 8.19 has the advantage of reduced computation time
compared to the R-C approach illustrated in Fig. 8.18. For n rows and 2n − 1 columns of
partial products, the summation time for an iterative CS (ICS) multiplier is
t
ICS
= (n − 2)t
FA
+ t
R−C
, (8.10)
where t
FA
is the delay of a FA and t
R−C
is the time required for the R-C adder to complete
the summation. In comparison, the summation time required for a multiplier that uses ...