
8.10 VHDL DESCRIPTION OF ARITHMETIC DEVICES 383
description of a four-bit adder composed of four full adders described in the previous
example. If Fig. 8.49 is used with reference to Figs. 8.4 and 8.5, the structure of the four-bit
adder is given as follows:
entity four
bit adder is
port (a0, a1, a2, a3, b0, b1, b2, b3, ci: in bit; s0, s1, s2, s3, co: out bit;
end four
bit adder;
architecture connect
four of four bit adder is
component full
adder
port (a, b, ci: in bit; s, co: out bit);
end component;
for all: full
adder use entity full adder example;
signal c1, c2, c3: bit
begin
FA0: full
adder port map (a0, b0, ci, s0, c1);
FA1: full
adder port map (a1, b1, c1, ...