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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
444 CHAPTER 10 / INTRODUCTION TO SYNCHRONOUS STATE MACHINE DESIGN
FIGURE 10.27
The FET D latch. (a) State diagram showing condition for transparency. (b) Logic circuit assuming
the use of a set-dominant basic cell as the memory for design. (c) Logic circuit symbol.
triggered device consistent with Fig. 10.20(b). A CK(H) or CK(L) simply means RET or
FET, respectively.
If either the RET D latch or the FET D latch is to be used as the memory element in the
design of a synchronous FSM, extreme care must be taken to ensure that the transparency
effect does not occur. Transparency effects in flip-flops result in unrecoverable errors and
must be avoided. This ...
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Publisher Resources

ISBN: 9780126912951