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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
10.7 THE D FLIP-FLOPS: GENERAL 449
FIGURE 10.33
The master–slave (MS) D flip-flop. (a) State diagram for the master and slave stages. (b) Logic circuit.
(c) Circuit symbol.
as the master stage and an FET D latch as the slave stage. The output of the master stage is
the input to the slave stage. Thus, the transparency problem of the D latch in Fig. 10.24a has
been eliminated by the addition of the slave stage that is triggered antiphase to the master.
Thus, should signals pass through the master stage when CK is active, they would be held
up at the slave stage input until CK goes inactive.
The design of the MS D flip-flop can be carried out following the ...
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Publisher Resources

ISBN: 9780126912951