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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
450 CHAPTER 10 / INTRODUCTION TO SYNCHRONOUS STATE MACHINE DESIGN
FIGURE 10.35
(a) The MS D flip-flop configured with CMOS transmission gates and inverters and requiring two-
phase (2) clocking. (b) The reset-dominant basic cell used to generate 2 clocking as indicated by
the output logic waveforms.
triggered antiphase to the master. However, there is the possibility of noise transfer, though
of low probability. If logic noise should appear at the input to the slave stage just at the
instant that CK goes through a falling edge, that noise can be transferred to the output.
One important advantage the MS D flip-flop has over the edge triggered variety
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Publisher Resources

ISBN: 9780126912951