
460 CHAPTER 10 / INTRODUCTION TO SYNCHRONOUS STATE MACHINE DESIGN
The external hardware requirememts in the design of the FET ST flip-flop can be min-
imized by using an RET JK flip-flop as the memory in place of a D flip-flop. If the D
excitation table in Fig. 10.46c is replaced by that for the JK flip-flops in Fig. 10.40c, the NS
functions become J = S + T and K =
¯
S, a reduction of one gate. It is left to the reader to
show the mapping details.
A Special-Purpose Clocked SR Latch As used in this text, the term latch refers to
gated or clocked memory elements that do not have data lockout character and that exhibit
transparency, or that lose their mixed-rail ...