
10.9 LATCHES AND FLIP-FLOPS WITH SERIOUS TIMING PROBLEMS 461
FIGURE 10.48
The D data lockout flip-flop. (a) All edge triggered flip-flop variety. (b) Same as (a) except with an
FET D latch as the slave stage.
reset-dominant basic cell yields the logic circuit and circuit symbol shown in Fig. 10.47e.
Clearly, an S,R = 1,1 condition cannot be delivered to the basic cell output stage. But there
is a partial transparency effect. For example, a change
¯
S
¯
R → S
¯
R while in state 0 with CK
active (CK = 1) will cause a transition to state 1 where Q is issued. Thus, Q follows S in
this case, which is a transparency effect. Similarly, a change
¯
S
¯
R →
¯
SR while in state ...