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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
10.10 ASYNCHRONOUS PRESET AND CLEAR OVERRIDES 463
Here, a handshake configuration exists between the master and slave stages. A handshake
configuration occurs when the output of one FSM is the input to another and vice versa. This
FSM is susceptible to a serious error catching problem: In the reset state, if CK is active
and a glitch or pulse occurs on the J input to the master stage, the master stage is irreversibly
set, passing that set condition on to the slave stage input. Then when CK goes inactive, the
output is updated to the set state. This is called 1’s catching and is an unrecoverable error,
since the final set state was not regulated by CK. Similarly, in the set state, if CK is active
and a glitch or pulse occurs on the K input, the master ...
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Publisher Resources

ISBN: 9780126912951