476 CHAPTER 10 / INTRODUCTION TO SYNCHRONOUS STATE MACHINE DESIGN
example, if the FSM should power up into don’t care state 110 with X inactive (
¯
X), it
would transit to state 111 on the next clock triggering edge and would falsely issue an
output Z if X goes active. Ideally, on power-up, this FSM should be initialized into state
000 to properly begin the sequence. Section 11.7 discusses the details by which this can be
accomplished.
10.13 ANALYSIS OF SIMPLE STATE MACHINES
The purpose of analyzing an FSM is to determine its sequential behavior and to identify
any problems it may have. The procedure for FSM analysis is roughly the reverse of the
procedure for FSM design given in Section 10.6. Thus, in a general sense, one begins with
a logic circuit ...