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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
488 CHAPTER 10 / INTRODUCTION TO SYNCHRONOUS STATE MACHINE DESIGN
10.15 Design the FSM in Fig. P10.7b by using PK flip-flops that are characterized by the
excitation table in Fig. P10.5b. To do this, find the gate-minimum logic required for
the NS- and output-forming logic. Do not implement the result. Thus, the information
in Figs. P10.7b and P10.5b must be brought together via the mapping algorithm in
Section 10.6. (Hint: The easiest approach to this problem is to obtain the NS K-maps
for a D flip-flop design and then apply the conversion logic for D-to-PK K-map
conversion. See Subsection 10.12.2 for assistance if needed.)
10.16 (a) Construct a four-state state diagram for an FSM that samples (with clock) a
continuous stream of data on an input X. The ...
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Publisher Resources

ISBN: 9780126912951