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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
11.3 DETECTION AND ELIMINATION OF STATIC HAZARDS 499
D flip-flop. Notice that one-half of a clock cycle is lost because of the action of the filter. If
the D flip-flop is triggered in phase with the FSM memory flip-flops, an entire clock cycle
will be lost in the filtering process. To help understand how the filtering process eliminates
logic noise such as ORGs, the following is presented for reference purposes:
Remember: All forms of logic noise (glitches), including ORGs, occur immediately
following the triggering edge of the clock waveform, and the duration of any logic
noise pulse will always be much less than one-half the clock period.
Because logic noise ...
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Publisher Resources

ISBN: 9780126912951