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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
11.5 CLOCK SKEW 517
flip-flop technology and by creating a large T
CK
for the synchronizers relative to the FSM,
large values of the MTBF can be achieved even with high frequencies. Note that use of a
delay circuit in place of the counter would be worse than having no delay at all. A divide-
by-2 counter doubles the clock period (see Subsection 12.3.1). Now, the clock period for
the two synchronizers is at least double that of the FSM, greatly improving chances for
2T
CK
>t
m
. The divide-by-2 counter should be the slow 74SL74 with a Q(L) D(H )
feedback as indicated in the insert to Fig. 11.23a. If this is not sufficient, there are other
alternatives. One alternative is to replace the divide-by-2 counter in Fig. 11.23a by a divide-
by-4 ripple counter
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Publisher Resources

ISBN: 9780126912951