
520 CHAPTER 11 / SYNCHRONOUS FSM DESIGN CONSIDERATIONS
a circuit or programming the routing paths in FPGAs. Try to avoid obvious sources of
asymmetric path delays, particularly those associated with the system clock leads. Often, a
conscious effort in this regard can save much time and expense.
11.6 CLOCK SOURCES AND CLOCK SIGNAL SPECIFICATIONS
Various timing problems relative to the clock waveform have been discussed, but no mention
has been made of the clock signal source and specifications. How, in fact, is a high-frequency,
highly precise clock waveform produced, and how must it be specified so as to perform
predictably as the system clock to a