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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
522 CHAPTER 11 / SYNCHRONOUS FSM DESIGN CONSIDERATIONS
FIGURE 11.27
Propagation delay data for an RET D flip-flop from which the maximum propagation delay can be
obtained.
sufficient information to evaluate Eq. (11.6), providing that acceptable values for τ
ns
max
and
t
fs
are used. The value for τ
ns
max
must be obtained with knowledge of the NS logic technol-
ogy, which is usually available from the manufacturer. An acceptable value for t
fs
might
be 20% of (τ
ff
+τ
ns
+t
su
)
max
, giving T
CK
= 1.2(τ
ff
+τ
ns
+t
su
)
max
as a safe minimum clock
period. Then from this, a safe maximum clock frequency f
CK
= 1/T
CK
can be obtained.
11.6.3 Buffering and Gating the Clock
There are other ...
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Publisher Resources

ISBN: 9780126912951