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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
536 CHAPTER 11 / SYNCHRONOUS FSM DESIGN CONSIDERATIONS
FIGURE 11.39
Implementation of Eqs. (11.10) for the one- to three-pulse generator showing the debouncing, syn-
chronizing, and initialization circuits.
Sanity(L) is connected to the active low asynchronous clear overrides of the flip-flops for
initialization or reset into the 000 state. Also note that only one RET D flip-flop is used
for the synchronizing stage of the start switch input, S. A more robust synchronizing stage
would be one such as that illustrated in Fig. 11.23a.
Although discrete two-level logic is used in Fig. 11.39 for the NS- and output-forming
logic, there exists a variety of other ...
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Publisher Resources

ISBN: 9780126912951