Skip to Main Content
Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
556 CHAPTER 11 / SYNCHRONOUS FSM DESIGN CONSIDERATIONS
timing diagram, the four BCD code bits will appear in reverse order since they
are introduced LSB first.)
(d) Verify the timing diagram of part (c) by simulating the logic circuit of part (a).
11.11 A 3-bit serial odd-parity detector is to be designed that will issue an active output
pulse P
Odd Det
(L) any time a series of three clock periods samples an odd number
of active pulses (one or three, in any order) on an input pulse string X. The output
must be issued only when clock is active.
(a) Construct an optimum state diagram and state table for this detector. To do
this, make effective use of the ...
Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Top-Down Digital VLSI Design

Top-Down Digital VLSI Design

Hubert Kaeslin
Engineering Physics

Engineering Physics

S. Mani Naidu
Analog Integrated Circuit Design, 2nd Edition

Analog Integrated Circuit Design, 2nd Edition

Tony Chan Carusone, David A. Johns, Kenneth W. Martin
Analog Circuit Design Volume Three

Analog Circuit Design Volume Three

Bob Dobkin, John Hamburger

Publisher Resources

ISBN: 9780126912951