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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
FIGURE 12.16
NS and output K-maps for the T or JK flip-flop design of the cascadable BCD counter in Fig. 12.15.
577
FIGURE 12.17
(a) Implementation of the 4-bit cascadable BCD up-counter by using FET JK flip-flops. (b) Cascaded
4-bit modules to produce a k-digit BCD counter.
FIGURE 12.18
Timing diagram for the BCD up-counter of Fig. 12.17 showing the frequency division and duty cycle
percentages for the state variables, and the output CO in state 1001.
578
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Publisher Resources

ISBN: 9780126912951